Core Utilization

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Core utilization is the amount of core area used by macros and standard cells on a semiconductor chip. It is defined as,

(Area of Standard Cells)+(Area of Macros)/(Total core area of the chip)

Ideally, we would like this to be 100% however, in practice we can expect to get a core utilization of 80-85%. By the end of the placement stage, we would want to achieve a core utilization of about 60-75%. This is because cells are added and upsized during CTS and STA. So by tape-out, we would reach a core utilization of around the expected 80-85%. The remaining 20% area can be used for routing.

Achieving high core utilization is generally not mandatory. We can try to achieve high core utilization if there is sufficient time for the chip to be released. For chips that have a tight deadline we can release the chip with an even lower value of core utilization provided the required functionality and performance are obtained.